The present invention relates generally to memory devices and in particular the present invention relates to reduction of drain stress in memory devices.
Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicates a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write.
Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. The transistors can be erased to restore the threshold voltage of the transistor. The memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. These non-volatile memory devices are commonly referred to as flash memories.
The non-volatile memory cells are fabricated as floating gate memory cells and include a source region and a drain region that is laterally spaced apart from the source region to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and can also made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is xe2x80x9cfloatingxe2x80x9d in dielectric so that it is insulated from both the channel and the control gate.
In flash memories of current design, block erase functions are used to erase selected blocks of the memory. This is accomplished as is known in the art by splitting a common diffused source, formerly for an entire memory array, into source blocks of predetermined size. This size is dependent upon the function of the memory. Each block of a memory array of this type is independently erasable.
To erase a block, a first voltage value is applied on the source of the selected block, a second voltage value is applied on all the control gates (wordlines) of the selected block, the substrate is grounded and the drains for all the cells (bitlines) are allowed to float. The first voltage applied on the source is in the range 0 to 12 V. The second voltage applied on control gates is in the range of xe2x88x9212 V to 0. In certain array architectures, multiple source blocks are stacked along a single bitline, that is, one bitline is connected to multiple erase blocks. In this configuration, the drains of the cells in several blocks are shared. Non-selected blocks, then, face a drain stress because they have a voltage on the drain that is used in programming selected blocks, but is still present because of the shared bitline on non-selected blocks.
Further, there is a potential problem of current leakage in columns, due to the common source and the voltages typically placed on source, drain, and gate during programming. Current may leak from the source of the unselected block to the source of the selected block sue to the voltage differences between the two sources.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing the drain stress on non-selected cells in a flash memory program operation.
The above-mentioned problems with drain disturb and soft programming in flash memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of programming a flash memory includes reducing drain stress on unselected blocks in the memory during programming, and reducing current leakage from unselected source blocks to selected source blocks during programming.
In another embodiment, a method of programming a flash memory includes selecting blocks of the memory having cells to be programmed, and applying potentials to the various inputs of the memory. The potentials are approximately 4 volts to 5 volts above a main memory ground potential to selected bitlines, approximately 1.5 volts to 2.5 volts above the main memory ground potential to source regions and wordlines of cells in non-selected blocks, approximately 0.5 volts to 2.5 volts above the main memory ground potential to non-selected bitlines, approximately 0.5 volts to 2 volts above the main memory ground potential to source regions of selected blocks, and approximately 0 volts to 2 volts above the main memory ground potential to non-selected wordlines in selected blocks.
In yet another embodiment, a memory device includes an array of non-volatile memory cells arranged in a patterns of rows and columns, a number of wordlines each connected to multiple cells in a row of cells, a number of bitlines each connected to multiple cells in a column of cells, and control circuitry to adjust voltages on memory array inputs during a programming function.
In still another embodiment, a flash memory device includes an array of floating gate memory cells, and control circuitry to read, write and erase the floating gate memory cells. The control circuitry includes a command module to adjust voltages on memory array inputs during a programming function.
In still yet another embodiment, a processing system includes a processor and a memory device coupled to the processor to store data provided by the processor and to provide data to the processor. The memory device includes an array of non-volatile memory cells arranged in a patterns of rows and columns, a number of wordlines each connected to multiple cells in a row of cells, a number of bitlines each connected to multiple cells in a column of cells, and control circuitry to adjust voltages on memory array inputs during a programming function.
Other embodiments are described and claimed.